Lab location: Hudson Hall 214
Instructor: Dr. Rabih Younes
Duke e-mail: rabih.younes
Instructor 1-on-1 office hours are available by appointment (link to make appointments on our Canvas homepage).
To provide anonymous feedback about anything related to the course, please follow the link provided on our Canvas homepage.
Teaching Assistants (TAs):
- Xuan Liu — Lead TA for projects
- Endong Dai — Lead TA for recitations
- Xiaotian Tong — Lead TA for student support
Course Description
Fundamentals of computer systems and engineering for Master's students whose undergraduate background did not cover this material. Topics covered include: Digital logic, assembly programming, computer architecture, memory hierarchies and technologies, IO, and hardware implementation in HDL. Undergraduates may not take this course, and should take ECE 250D, ECE 353, and/or ECE 356 instead. Not open to students who have taken or are taking ECE 552.Learning Outcomes
Having successfully completed this course, the student will be able to:- design combinational and sequential circuits at the transistor (CMOS) and gate/logic levels;
- implement, simulate, and test logic circuits;
- use Verilog hardware description language;
- write programs using Assembly language;
- describe and analyze how computer memory operates;
- describe the basic operations of IO devices, interrupts, and exceptions; and
- design, implement, and test a processor.
Textbook and Other Course Material
Textbook not required. One suggested textbook is: David A. Patterson and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, 5th edition, Morgan-Kaufmann. (Amazon, AddAll) — (Not the "ARM" edition or the "Revised Printing").All needed material will be posted on Canvas.
Grading Policy
- Recitations (15%): Recitations are sessions for hands-on practice using software and hardware tools. Grades are based on completion (must demonstrate working module to TA).
- Exam 1 (20%).
- Exam 2 (20%).
- Project (40%): Checkpoints that build up to implementing a processor.
- Project checkpoint 1 (Simple ALU): 6%
- Project checkpoint 2 (Full ALU): 7%
- Project checkpoint 3 (Register File): 7%
- Project checkpoint 4 (Simple Processor): 10%
- Project checkpoint 5 (Full Processor): 10%
- Project checkpoint 6 (Interactive Game): +5 extra credit points on the final course grade
- Concept maps (5%): Pre- and post-course concept maps to help measure and reflect on learning.
- NO FINAL EXAM!
- Late policy: Late submissions are not allowed unless you have a valid excuse. In that case, email your instructor about it as soon as possible and wait for a decision (might involve a penalty, depending on the excuse). Refer to this list of common but unacceptable excuses borrowed from Dr. Bletsch.
- Regrading policy: Regrading must be requested no later than one week after the assignment grade is released.
- Grading schema:
- ≥ 97.00: A+
- ≥ 93.00: A
- ≥ 90.00: A-
- ≥ 87.00: B+
- ≥ 83.00: B
- ≥ 80.00: B-
- ≥ 77.00: C+
- ≥ 73.00: C
- ≥ 70.00: C-
- < 70.00: F
Important Notes
Extremely important advice:
We can only grade what we receive. Always check what you are submitting and make sure you submit the right files.
Contacting the instructor and the TAs:
- For questions that can be answered by a TA or the instructor: use Ed Discussion
- To contact a specific TA or the instructor: use email (do not use texting, social media, ...)
Misconduct
- Academic misconduct will not be tolerated and will be taken very seriously.
- You are expected to complete the assignments individually unless otherwise stated.
- Students are encouraged to share ideas, learn from each other, and learn from online sources, but cheating is not tolerated.
- Any borrowed design/code/etc. — if allowed to be borrowed — should be properly cited.
- Students suspected violating the Duke Community Standard will be reported.
- In addition to the measures taken by the administration, the affected assignment(s) will receive zero credit, or possibly -100% in extreme cases.
- If you are considering this course of action, please see me instead and we can discuss it further. I want every student in my course to be successful.
- Note that assignment submissions will be compared to one another and to previous work using plagiarism detection software.
Tentative Schedule
| Week | Day | Topic | Project Checkpoint Due | Recitation (Fridays, in teams of 2) |
|---|---|---|---|---|
| 1 | Tu 8/25 | Syllabus | ||
| 1 | Th 8/27 | Intro | Quartus + Verilog Intro | |
| 2 | Tu 9/1 | Transistor-Level Design | ||
| 2 | Th 9/3 | Gate-Level Design | Adder | |
| 3 | Tu 9/8 | Digital Arithmetic | ||
| 3 | Th 9/10 | Digital Arithmetic | Multiplier | |
| 4 | Tu 9/15 | Storage and Clocking | Simple ALU (PC1) | |
| 4 | Th 9/17 | Finite State Machines | FSM | |
| 5 | Tu 9/22 | NO CLASS | ||
| 5 | Th 9/24 | Practice Problems | Full ALU (PC2) | Behavioral Verilog |
| 6 | Tu 9/29 | ISA | ||
| 6 | Th 10/1 | ISA | FPGA Board Intro | |
| 7 | Tu 10/6 | Datapath | Register File (PC3) | |
| 7 | Th 10/8 | Datapath + Clock Division + FPGAs | I/O Interfacing: PS2 | |
| 8 | Tu 10/13 | NO CLASS (Fall Break) | ||
| 8 | Th 10/15 | Exam 1 Review + Practice | Exam 1 [beginning - Datapath] | |
| 9 | Tu 10/20 | Exam 1 Muddiest Points | ||
| 9 | Th 10/22 | Pipelining | Work on processor | |
| 10 | Tu 10/27 | Pipelining | Simple Processor (PC4) (in teams of 2) | |
| 10 | Th 10/29 | Memory Hierarchy | I/O Interfacing: VGA | |
| 11 | Tu 11/3 | Memory Hierarchy | ||
| 11 | Th 11/5 | Virtual Memory | Work on processor | |
| 12 | Tu 11/10 | Virtual Memory | ||
| 12 | Th 11/12 | OS | Work on processor | |
| 13 | Tu 11/17 | Interrupts + I/O | Full Processor (PC5) (in teams of 2) | |
| 13 | Th 11/19 | Exam 2 Review + Practice | Exam 2 [Pipelining - I/O] | |
| 14 | Tu 11/24 | NO CLASS | ||
| 16 | 12/9-11 | NO FINAL EXAM | Interactive Game (PC6) Demo (in teams of 2-3) |