ECE 550D
Fundamentals of Computer Systems and Engineering
Fall 2023

based on a diagram by Dr. Tyler Bletsch
Class meeting times and location: Recitation meeting time and location: Fr 11:45am–1:00pm — FITZPATRICK SCHICIANO B 1466
Lab location: Hudson Hall 214

Instructor: Dr. Rabih Younes
Duke e-mail: rabih.younes
Instructor 1-on-1 office hours are available by appointment (link to make appointments posted on Canvas).
To provide anonymous feedback about anything related to the course, please follow this link (password posted on Canvas).

Teaching Assistants (TAs): TA office hours (location: Hudson Hall 214):

Course Description

Fundamentals of computer systems and engineering for Master's students whose undergraduate background did not cover this material. Topics covered include: Digital logic, assembly programming, computer architecture, memory hierarchies and technologies, IO, and hardware implementation in HDL. Undergraduates may not take this course, and should take ECE 250D, ECE 353, and/or ECE 356 instead. 3 units. Co-requisite: ECE 551D.

Learning Outcomes

Having successfully completed this course, the student will be able to:

Textbook and Other Course Material

Textbook not required. One suggested textbook is: David A. Patterson and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, 5th edition, Morgan-Kaufmann. (Amazon, AddAll) — (Not the "ARM" edition or the "Revised Printing").
All needed material will be posted on Canvas.

Grading Policy

Important Notes

Extremely important advice:

We can only grade what we receive. Always check what you are submitting and make sure you submit the right files.

Contacting the instructor and the TAs:


Communications Support at Pratt

Graduate Communications and Intercultural Programs (GCIP) offers customized communications support for all graduate students at Pratt. They offer one-on-one coaching in the Graduate Communications Center (GCC) for all communications needs (e.g., academic writing, cover letters, presentations, pronunciation, master's theses/projects, PhD dissertations/publication/prelims). Additionally, GCIP offers a communication workshop series to help build specific communication skills throughout the academic year. Visit this link or email

Tentative Schedule

Week Date Topic Project Checkpoint Due Recitation (Fridays, in teams of 2)
1 Tu 8/29 Syllabus + Intro
1 Th 8/31 From Transistors to Gates Quartus + Verilog Intro
2 Tu 9/5 Combinatorial Logic
2 Th 9/7 Digital Arithmetic Adder
3 Tu 9/12 Digital Arithmetic
3 Th 9/14 Storage and Clocking Multiplier
4 Tu 9/19 Finite State Machines
4 Th 9/21 ISA Simple ALU (PC1) FSM
5 Tu 9/26 ISA
5 Th 9/28 Datapath Behavioral Verilog
6 Tu 10/3 Datapath Full ALU (PC2)
6 Th 10/5 Clock Division + FPGAs + Exam 1 Review FPGA Board Intro
7 Tu 10/10 Practice Problems (professor traveling) Register File (PC3)
7 Th 10/12 Practice Problems (professor traveling) Exam 1 [beginning - Datapath]
8 Tu 10/17 NO CLASS (Fall Break)
8 Th 10/19 Exam 1 Muddiest Points + Pipelining I/O Interfacing: PS2
9 Tu 10/24 Pipelining
9 Th 10/26 Memory Hierarchy Work on processor
10 Tu 10/31 Practice Problems (professor traveling) Simple Processor (PC4) (in teams of 2)
10 Th 11/2 Memory Hierarchy I/O Interfacing: VGA
11 Tu 11/7 Virtual Memory
11 Th 11/9 Virtual Memory Work on processor
12 Tu 11/14 Interrupts, Exceptions, and System Calls
12 Th 11/16 OS Work on processor
13 Tu 11/21 I/O Full Processor (PC5) (in teams of 2)
13 Th 11/23 NO CLASS (Thanksgiving Recess)
14 Tu 11/28 Practice Problems
14 Th 11/30 Exam 2 Review Exam 2 [Pipelining - I/O]
16 Fri 12/15 NO CLASS Interactive Game (PC6) Demo (in teams of 2-3)