- Section 1: TuTh 10:05–11:20am — Wilkinson 126
- Section 2: TuTh 1:25–2:40pm — Teer 106
Lab location: Hudson Hall 214
Instructor: Dr. Rabih Younes
Duke e-mail: rabih.younes
Instructor 1-on-1 office hours are available by appointment (link to make appointments posted on Canvas).
To provide anonymous feedback about anything related to the course, please follow this link (password posted on Canvas).
Teaching Assistants (TAs):
- Rui Cao (rc384) — Head TAs for projects
- Yang Xu (yx248) — Head TA for project autograding
- Fan Yang (fy62) — Head TA for recitations
- Yuanjia Wang (yw520) — Head TA for grading
- Hangming Ye (hy201) — Head TA for online student questions
- Can Pei (cp357) — Head TA for plagiarism checking
- MoWe: 12:15–1:15 (2 TAs)
- TuTh: 11:30–1:15 & 2:45–4:00 (2-4 TAs)
Course Description
Fundamentals of computer systems and engineering for Master's students whose undergraduate background did not cover this material. Topics covered include: Digital logic, assembly programming, computer architecture, memory hierarchies and technologies, IO, and hardware implementation in HDL. Undergraduates may not take this course, and should take ECE 250D, ECE 353, and/or ECE 356 instead. 3 units. Co-requisite: ECE 551D.Learning Outcomes
Having successfully completed this course, the student will be able to:- design combinational and sequential circuits at the transistor (CMOS) and gate/logic levels;
- implement, simulate, and test logic circuits;
- use Verilog hardware description language;
- write programs using Assembly language;
- describe and analyze how computer memory operates;
- describe the basic operations of IO devices, interrupts, and exceptions; and
- design, implement, and test a processor.
Textbook and Other Course Material
Textbook not required. One suggested textbook is: David A. Patterson and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, 5th edition, Morgan-Kaufmann. (Amazon, AddAll) — (Not the "ARM" edition or the "Revised Printing").All needed material will be posted on Canvas.
Grading Policy
- Recitations (15%): Recitations are sessions for hands-on practice using software and hardware tools. Grades are based on completion (must demonstrate working module to TA).
- Exam 1 (20%).
- Exam 2 (20%).
- Project (40%): Checkpoints that build up to implementing a processor.
- Project checkpoint 1 (Simple ALU): 6%
- Project checkpoint 2 (Full ALU): 7%
- Project checkpoint 3 (Register File): 7%
- Project checkpoint 4 (Simple Processor): 10%
- Project checkpoint 5 (Full Processor): 10%
- Project checkpoint 6 (Interactive Game): +5 extra credit points (on the final course grade)
- Concept maps (5%): Pre- and post-course concept maps to help measure learning.
- NO FINAL EXAM!
- Late policy: Late submissions are not allowed unless you have a valid excuse. In that case, email your instructor about it as soon as possible and wait for a decision (might involve a penalty, depending on the excuse). Refer to this list of common but unacceptable excuses borrowed from Dr. Bletsch's webpage.
- Regrading policy: Regrade requests must be submitted no later than one week after the assignment grade is released.
- Grading schema (minimum %):
- 97: A+
- 93: A
- 90: A-
- 87: B+
- 83: B
- 80: B-
- 77: C+
- 73: C
- 70: C-
- 0: F
Important Notes
Extremely important advice:
We can only grade what we receive. Always check what you are submitting and make sure you submit the right files.
Contacting the instructor and the TAs:
- For questions that can be answered by any TA or the instructor: use Ed Discussion
- To contact a specific TA or the instructor: use email (do not use texting, social media, ...)
Misconduct
- Academic misconduct will not be tolerated and will be taken very seriously.
- You are expected to complete the assignments individually unless otherwise stated.
- Students are encouraged to share ideas, learn from each other, and learn from online sources, but cheating is not tolerated.
- Any borrowed design/code/etc. — if allowed to be borrowed — should be properly cited.
- Students suspected violating the Duke Community Standard will be reported.
- In addition to the measures taken by the administration, the affected assignment(s) will receive zero credit, or possibly -100% in extreme cases.
- If you are considering this course of action, please see me instead, and we can work something out! I want every student in my course to be successful.
- Note that programming submissions will be compared to one another and to previous semesters using Stanford's Measure of Software Similarity (MOSS) to detect signs of plagiarism.
Communications Support at Pratt
Graduate Communications and Intercultural Programs (GCIP) offers customized communications support for all graduate students at Pratt. They offer one-on-one coaching in the Graduate Communications Center (GCC) for all communications needs (e.g., academic writing, cover letters, presentations, pronunciation, master's theses/projects, PhD dissertations/publication/prelims). Additionally, GCIP offers a communication workshop series to help build specific communication skills throughout the academic year. Visit this link or email gcc-pratt@duke.edu.Tentative Schedule
| Week | Date | Topic | Project Checkpoint Due | Recitation (Fridays, in teams of 2) |
|---|---|---|---|---|
| 1 | Tu 8/29 | Syllabus + Intro | ||
| 1 | Th 8/31 | From Transistors to Gates | Quartus + Verilog Intro | |
| 2 | Tu 9/5 | Combinatorial Logic | ||
| 2 | Th 9/7 | Digital Arithmetic | Adder | |
| 3 | Tu 9/12 | Digital Arithmetic | ||
| 3 | Th 9/14 | Storage and Clocking | Multiplier | |
| 4 | Tu 9/19 | Finite State Machines | ||
| 4 | Th 9/21 | ISA | Simple ALU (PC1) | FSM |
| 5 | Tu 9/26 | ISA | ||
| 5 | Th 9/28 | Datapath | Behavioral Verilog | |
| 6 | Tu 10/3 | Datapath | Full ALU (PC2) | |
| 6 | Th 10/5 | Clock Division + FPGAs + Exam 1 Review | FPGA Board Intro | |
| 7 | Tu 10/10 | Practice Problems (professor traveling) | Register File (PC3) | |
| 7 | Th 10/12 | Practice Problems (professor traveling) | Exam 1 [beginning - Datapath] | |
| 8 | Tu 10/17 | NO CLASS (Fall Break) | ||
| 8 | Th 10/19 | Exam 1 Muddiest Points + Pipelining | I/O Interfacing: PS2 | |
| 9 | Tu 10/24 | Pipelining | ||
| 9 | Th 10/26 | Memory Hierarchy | Work on processor | |
| 10 | Tu 10/31 | Practice Problems (professor traveling) | Simple Processor (PC4) (in teams of 2) | |
| 10 | Th 11/2 | Memory Hierarchy | I/O Interfacing: VGA | |
| 11 | Tu 11/7 | Virtual Memory | ||
| 11 | Th 11/9 | Virtual Memory | Work on processor | |
| 12 | Tu 11/14 | Interrupts, Exceptions, and System Calls | ||
| 12 | Th 11/16 | OS | Work on processor | |
| 13 | Tu 11/21 | I/O | Full Processor (PC5) (in teams of 2) | |
| 13 | Th 11/23 | NO CLASS (Thanksgiving Recess) | ||
| 14 | Tu 11/28 | Practice Problems | ||
| 14 | Th 11/30 | Exam 2 Review | Exam 2 [Pipelining - I/O] | |
| 16 | Fri 12/15 | NO CLASS | Interactive Game (PC6) Demo (in teams of 2-3) |