ECE 550D: Fundamentals of Computer Systems and Engineering — Fall 2020
Class meeting times and location: TTh 10:15–11:30AM and 10:00–11:15PM (2 sections) — Zoom
Recitation meeting times and location: F 10:00–11:15AM, 7:00–8:15PM, and 8:30–9:45PM — Zoom
based on a diagram by Dr. Tyler Bletsch
Instructor: Dr. Rabih Younes
Duke e-mail: rabih.younes
Office hours: by appointment (link to make appointments and receive Zoom link posted on Sakai)
To provide anonymous feedback about anything related to the course, please follow this link (password posted on Sakai).
TAs:
- Yifan (Eunbi) Zhang (yz553) — Head TA for project and recitations
- Bokyung Kim (bk174) — Head TA for homework and grading
TAs office hours (location: Zoom):
- M, T, W, and Th 10–11AM: Eunbi (yz553)
- M, T, W, and Th 9–10PM: Bokyung (bk174)
Course Description
Fundamentals of computer systems and engineering for Master's students whose undergraduate background did not cover this material. Topics covered include: Digital logic, assembly programming, computer architecture, memory hierarchies and
technologies, IO, and hardware implementation in HDL. Undergraduates may not take this course, and should take ECE 250D, ECE 353, and/or ECE 356 instead. Instructor: Younes. 3 units. Co-requisite: ECE 551D.
Learning Outcomes
Having successfully completed this course, the student will be able to:
- design combinational and sequential circuits at the transistor (CMOS) and gate/logic levels;
- implement, simulate, and test logic circuits;
- use Verilog hardware description language;
- write programs using Assembly language;
- describe and analyze how computer memory operates;
- describe the basic operations of IO devices, interrupts, and exceptions; and
- design, implement, and test a processor.
Textbook and Other Course Material
Textbook not required. The suggested textbook is: David A. Patterson and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, 5th edition, Morgan-Kaufmann. (Amazon,
AddAll) —
(Not the "ARM" edition or the "Revised Printing").
All other material will be posted on Sakai. Slides will be posted before class time so that you can take notes on them if you would like to.
Grading Policy
- Recitations (10%): Recitations are sessions for hands-on practice using Quartus and Modelsim. Grades are based on completion (must demonstrate working module to TA).
- Homeworks (20%): About 5 homeworks (check the schedule below).
- Exam 1 (15%).
- Exam 2 (15%).
- Project (40%): Checkpoints that build up to implementing a processor.
- NO FINAL EXAM!
- Late policy: Late submissions are not allowed unless you have a valid excuse. In that case, email me about it as soon as possible and wait for a decision (might involve a penalty, depending on the excuse). Refer
to this list of common but unacceptable excuses borrowed from Dr. Bletsch's webpage.
- Regrading policy: Regrade requests must be submitted no later than one week after the assignment grade is released.
Important Notes
***Extremely important advice:
- Start as early as you can! Leave ample time for testing!
- Review class lectures after every class (or before the next one).
- Manage your time well and work on multiple assignments in parallel. Split bigger task into smaller (realistic) ones. Make sure you use a calendar and a to-do list.
- Use Git to keep track of previous versions of your work and use a cloud storage service to back up your work (GitLab, GitHub, etc.).
- Ask questions! We are here to help! We want you to succeed!
All announcements are posted on Piazza. Make sure you can receive Piazza email notifications.
We can only grade what we receive. Always check what you are submitting and make sure you submit the right files.
Contacting the instructor and the TAs:
- For questions that can be answered by any TA or the instructor: use Piazza
- To contact a specific TA or the instructor: use email (do not text, facebook, ...)
Misconduct
- Academic misconduct will not be tolerated and will be taken very seriously.
- You are expected to complete the assignments individually unless otherwise stated.
- Students are encouraged to share ideas, learn from each other, and learn from online sources, but cheating is not tolerated.
- Any borrowed design/code/etc. — if allowed to be borrowed — should be properly cited.
- Students suspected violating the Duke Community Standard will be reported.
- In addition to the measures taken by the administration, the affected assignment(s) will receive zero credit, or possibly -100% in extreme cases.
- If you are considering this course of action, please see me instead, and we can work something out! I want every student in my course to be successful.
- Note that programming submissions will be compared to one another and to previous semesters using Stanford's Measure of Software Similarity (MOSS) to detect signs of plagiarism.
Communications Support at Pratt
Graduate Communications and Intercultural Programs (GCIP) offers customized communications support for all graduate students at Pratt. They offer one-on-one coaching in the Graduate Communications Center (GCC) for all communications needs (e.g.,
academic writing, cover letters, presentations, pronunciation, master's theses/projects, PhD dissertations/publication/prelims). Additionally, GCIP offers a communication workshop series to help build specific communication skills throughout the
academic year. Visit this link or email gcc-pratt@duke.edu.
Week |
Date |
Topic |
Homework |
Project |
Recitation (Friday) |
1 |
Tue 8/18 |
Syllabus + Intro |
|
|
|
1 |
Thu 8/20 |
Transistors to Gates |
|
|
Quartus + Verilog Intro |
2 |
Tue 8/25 |
Combinational Logic |
|
|
|
2 |
Thu 8/27 |
Implementing Arithmetic |
|
|
Adder |
3 |
Tue 9/1 |
Storage and Clocking |
|
|
|
3 |
Thu 9/3 |
Finite State Machines |
1 due |
Simple ALU due |
Multiplier |
4 |
Tue 9/8 |
ISAs and MIPS |
|
|
|
4 |
Thu 9/10 |
ISAs and MIPS |
|
|
FSM |
5 |
Tue 9/15 |
Practice (professor attending conference) |
|
Full ALU due |
|
5 |
Thu 9/17 |
Practice (professor attending conference) |
2 due |
|
Behavioral Verilog |
6 |
Tue 9/22 |
ISAs and MIPS |
|
|
|
6 |
Thu 9/24 |
Datapaths |
|
|
Work on project |
7 |
Tue 9/29 |
Datapaths |
|
Register File due |
|
7 |
Thu 10/1 |
Exam 1 Review |
|
|
Work on project |
8 |
Tue 10/6 |
Exam 1 @TBD (weeks 1–7) |
|
|
|
8 |
Thu 10/8 |
Pipelining + Exam 1 Muddiest Points |
|
|
Work on project |
9 |
Tue 10/13 |
Pipelining |
|
|
|
9 |
Thu 10/15 |
Memory Hierarchy |
|
|
Work on project |
10 |
Tue 10/20 |
Memory Hierarchy |
3 due |
|
|
10 |
Thu 10/22 |
Memory Hierarchy |
|
Simple Processor due (in pairs) |
Work on project |
11 |
Tue 10/27 |
Virtual Memory |
|
|
|
11 |
Thu 10/29 |
Virtual Memory |
4 due |
|
Work on project |
12 |
Tue 11/3 |
Interrupts and Exceptions + I/O |
|
|
|
12 |
Thu 11/5 |
OS |
|
|
Work on project |
13 |
Tue 11/10 |
Exam 2 Review |
5 due |
|
|
13 |
Thu 11/12 |
Exam 2 @TBD (weeks 8–12) |
|
Full Processor due (in pairs) |
|