ECE/COMPSCI 350L: Digital Systems — Fall 2018

Class meeting time and location: TTh 10:05–11:20, Gross Hall 103

Lab meeting time and location: T 3:05–6:05, W 1:25–4:25, W 4:40–7:40, Th 11:45–2:45, Th 3:05–6:05, F 10:05–1:05, Hudson Hall 202A

Instructor: Dr. Rabih Younes
Duke e-mail: rabih.younes
Office: Hudson Hall 204
Office phone: 660-5051
Office hours: TTh 1:30–2:45, or by appointment

Head TA (course and labs): Kyle Finke (kyle.finke@duke.edu)
Head Course TA: Liz Pharis (elizabeth.pharis@duke.edu)
Course TAs: Nathaniel Brooke (nathaniel.brooke@duke.edu), Natalie Huffman (natalie.huffman@duke.edu), and Michael Scruggs (michael.scruggs@duke.edu)
Lab TAs:

Vishnu Gottiparthy (vishnu.gottiparthy@duke.edu) — T
Kyle Finke (kyle.finke@duke.edu) — W@1:25
John Fitzpatrick (jack.fitzpatrick@duke.edu) — W@4:40
Ken Koch (kenneth.koch@duke.edu) — Th@11:45
Liz Pharis (elizabeth.pharis@duke.edu) — Th@3:05
Matthew Dickson (matthew.d.dickson@duke.edu) — F

TAs office hours: M 6–8, T 6–8, W 6–8, and Th 4–8 — Hudson Hall 202A

Course Description

Design and implementation of combinational and sequential digital systems with special attention to digital computers. The use of computer-aided design tools, hardware description languages, and programmable logic chips to facilitate larger and higher performance designs will be stressed. Laboratory exercises and group design projects will reinforce the various design techniques discussed in class. Prerequisite: Electrical and Computer Engineering 250D. Instructor: Younes. One course.

Learning Outcomes

Having successfully completed this course, the student will be able to:

perform boolean algebra operations;
design combinational and sequential circuits at the circuit (CMOS) and gate/logic levels;
implement logic circuits on breadboards and FPGAs;
use Verilog hardware description language; and
design and implement a pipelined processor.

Textbook and Other Course Material

No textbook is required for this course. All material will be posted on Sakai (DO NOT repost/upload to any site; the material is copyrighted). I will always try to have slides posted before class time so that you can take notes on them if you would like to.

Grading Policy

Homeworks (10%): There will be weekly homeworks due on Tuesdays (with some exceptions, check the schedule below). The lowest grade will be dropped.
Quizzes (0%): There will be a 5-minute quiz every Tuesday (with some exceptions; check the schedule below). The objective of having these quizzes is to prepare you for the exams. The quizzes will not be graded but you are required to submit all quizzes during their class time.
Exam 1 (20%): Tentatively on 10/16. Covers weeks 1–6.
Exam 2 (15%): Tentatively on 11/29. Covers weeks 8–12.
Labs (10%): Completed in groups of two during lab section. Grades are based on completion (must demonstrate working circuit/module to lab TA). Lab reports are due every Thursday (with some exceptions; check the schedule below). You may come to any lab time/office hours to finish up a lab if you need to; make sure you communicate that with the corresponding labs' TAs.
Project checkpoints 1–4 (15%): Checkpoints to build a pipelined processor (regfile, ALU, multdiv, and processor). Written in Verilog (hardware description language).
Project checkpoints 5–10 (30%): include project proposal, demo, report, and other project checkpoints in between. The final project is open-ended, in groups of 2 or 3, and it includes the use of Verilog and Assembly.
NO FINAL EXAM!
Completion: All the above items require completion — as determined by the instructor/TAs — by the end of the semester. Even if you miss the deadline for an assignment (except for quizzes), you still must complete it and submit it. Otherwise, your final course grade will be reduced by a full letter grade.
Late policy: Late submissions are not allowed unless you have a valid excuse. In that case, contact the Head TA about it as soon as possible and wait for their decision.

Notes on using git, LaTeX, and Github:

Each pushed commit is considered a submission
Code not associated with a commit is not accepted
Submission time is when Github receives it
Each commit must follow academic conduct policies

Install Altera's Quartus and use it for labs and assignments.
Extremely important advice: Start as early as you can! Leave ample time for testing!

Misconduct

Students caught violating the Duke Community Standard will be reported to the Office of Student Conduct. Students are encouraged to share ideas, learn from each other, and learn from online sources, but cheating is not tolerated. Any borrowed design/code/etc. — if allowed to be borrowed — should be properly cited. Note that programming submissions will be compared to one another using Stanford's Measure of Software Similarity (MOSS) to detect signs of plagiarism (includes previous semesters' code).

Summary of Important Dates

10/16: Exam 1
11/29: Exam 2
12/6: Project demo due
12/7: Project report due

Detailed Schedule

Week	Date	Topic	Quiz	Homework	Project	Lab
1	8/28	Syllabus, Intro, Boolean Alg.				Lab 1 - Intro
1	8/30	Boolean Alg.
2	9/4	Logic Blocks	1	1 due		Lab 2 - Regfile
2	9/6	CAD & Verilog, Register				Lab 1 Report Due
3	9/11	Signed Arithmetic	2	2 due	PC 1 (regfile) due	Lab 3 - RCA
3	9/13	NO CLASS: Hurricane				Lab 2 No Report
4	9/18	Fast Adders & ALU, Multipliers				Lab 4 - Comparators
4	9/20	Booth's Algorithm, Division	3	3 due	PC 2 (alu) due	Lab 3 Report Due
5	9/25	Memory Elements	4			Lab 5 - Memory
5	9/27	Memory Elements		4 due		Lab 4 Report Due
6	10/2	Pipelining: Intro, Hazards	5			Lab 6 - VGA and PS2
6	10/4	Pipelining		5 due	PC 3 (multdiv) due	Lab 5 Report Due
7	10/9	NO CLASS: Fall Break				No lab
7	10/11	Review Session 1	6	6 due
8	10/16	Exam 1 (weeks 1–6)				Lab 7 - Audio
8	10/18	Factorization				Lab 6 Report Due
9	10/23	Factorization, Quine-McCluskey				Lab 8 - ADC
9	10/25	FSM	7	7 due		Lab 7 Report Due
10	10/30	FSM			PC 4 (proc) due / defense	Catch up
10	11/1	FSM, Async. Design		8 due	PC 5 (proposal) due
11	11/6	Async. Design	8			Lab 9 - Project
11	11/8	Async. Design, CMOS Design		9 due	PC 6 (check in) due	Lab 8 Report Due
12	11/13	CMOS Design, Defect Tolerance	9			Lab 10 - FSMs
12	11/15	Defect Tolerance, Testing		10 due	PC 7 (check in) due
13	11/20	NO CLASS (go through the "Gate Arrays" lecture)				Lab 10 Report Due
13	11/22	NO CLASS: Thanksgiving
14	11/27	Review Session 2	10	11 due	PC 8 (check in) due	Project Work
14	11/29	Exam 2 (weeks 8–12)
15	12/6	Project demos			PC 9 (demo) due	Project Work
15	12/7	Project demos			PC 10 (report) due
16	12/14	NO FINAL EXAM